1. Field of the Invention
The present invention relates to a double superheterodyne type radio frequency receiving circuit, in particular, to a PLL frequency synthesizer type receiving circuit.
2. Description of the Related Art
For example, in a radio frequency receiving circuit for use with a GPS (Global Positioning System), a double superheterodyne system that converts a received signal into a first intermediate frequency (IF) signal and a second intermediate frequency (IF) signal is most popularly used. On the other hand, the first IF frequency may accord with or be close to a frequency of a local FM broadcast in some regions. As mentioned later, a leakage of the first IF frequency of GPS receiver or an intrusion of an FM broadcast radio wave causes an intermodulation, resulting in degrading the accuracy of the received signal. In particular, since a GPS receiver has a high gain amplifier for the second intermediate frequency, the problem may need to change the frequency to another frequency. Thus, a conventional GPS receiver is operated with a fixed different frequency that depends on the region where the receiver is used. Consequently, it is difficult to accomplish a GPS receiver using identical IF frequency in the world wide.
FIG. 6 shows an example of the structure of such a GPS receiver as described in "Paper Machine .mu.PB1001GR" issued by NEC. An RF received signal (frequency: fRF) is supplied to an RF amplifier 11. The RF amplifier 11 amplifies the RF received signal. A first mixer 12 mixes the amplified RF received signal with an oscillation frequency f1LO of a voltage controlling oscillator (VCO) 16 that composes a first local oscillator (LO) and outputs a first IF signal (frequency: f1IF). The first IF signal is amplified by a first IF amplifier 13. A second mixer 14 mixes the amplified first IF signal with a frequency f2LO of a second LO and outputs a second IF signal (frequency: f2IF). The second IF signal is amplified by a second IF amplifier 15. The second IF signal is output to a demodulator or the like (not shown). The second LO is composed of a plurality of fixed frequency dividers (in this example, six frequency dividers) 24 to 29. By selecting one of output signals of the fixed frequency dividers, the frequency f2LO of the relevant second LO is obtained. An output signal of the fixed frequency divider 29 on the last stage is supplied to a phase comparator 22. The phase comparator 22 compares the output signal of the fixed frequency divider with an oscillation frequency fREF of a reference oscillator 20. With a compared result of an output signal of the reference oscillator 20 and the output signal of the fixed frequency divider 29, the oscillation frequency of the VCO 16 is controlled. In such a structure, a PLL synthesizer is accomplished.
In this structure, when the oscillation frequency of the VCO 16 is varied, the frequency f1LO of the first LO can be varied. Thus, the frequency f1IF of the first IF signal can be varied. However, to vary the oscillation frequency of the VCO 16, the oscillation frequency fRF of the reference oscillator 20 should be also varied. In addition, as the frequency f1IF of the first IF signal is varied, the frequency f2IF of the second IF signal is also varied. Thus, when one of the output signals of the fixed frequency dividers 24 to 28 is selected as an output signal of the second LO, the frequency f2IF of the second IF signal can not be fixed.
As another example of the structure of which a variable frequency divider is composed of a pulse swallow type counter is known. FIG. 7 shows such a structure. In this structure, instead of the fixed frequency dividers 24 to 29 shown in FIG. 6, two variable frequency dividers 30 and 31 are used. A VCO 16 outputs a signal with an oscillation frequency of a first LO. In addition, the oscillation frequency of the VCO 16 is divided by the first variable frequency divider 30. The reference oscillator 20 outputs a signal with an oscillation frequency of a second LO. In addition, the oscillation frequency of the reference oscillator 20 is divided by the second variable frequency divider 31. These frequencies of the output signals of the first and second variable frequency dividers 30 and 31 are compared by a phase comparator 22. Thus, the VCO is controlled. The frequency dividing values of the first and second variable frequency dividers 30 and 31 are controlled by a variable frequency controlling circuit 32. A variable frequency controlling circuit 32 can set a continuous integral dividing value to dividers 30 and 31 and can not set without the continuous integral dividing value.
By varying the oscillation frequency of the VCO 16, the frequency f1IF of the first IF signal can be varied. By controlling the frequency dividing value of the variable frequency divider 30 corresponding to the variation of the frequency of the first IF signal, the frequency f2IF of the second IF can be fixed. However, since the frequency of the second LO is fixed, as the frequency of the first IF signal is varied, the frequency fRF of the received signal is also varied. Thus, a signal with a desired frequency can not be received.
In the structure shown in FIG. 6, to vary the oscillation frequency of the VCO that is the first LO, the oscillation frequency of the reference oscillator should be varied at the same time. In addition, since the frequency f2IF of the second IF signal is fixed regardless of the variation of the frequency of the first IF signal, one of output signals of a plurality of fixed frequency dividers should be selected. However, actually, when an output signal of a small number of fixed frequency dividers is selected, the second IF frequency cannot be fixed to a predetermined constant frequency. Thus, the structure shown in FIG. 6 has a practical problem.
On the other hand, in the structure shown in FIG. 7, since the frequency f2LO of the second LO is fixed, if the frequency f1IF of the first IF signal is compulsorily varied, the frequency fRF of the received signal is varied. Thus, such a structure cannot be applied to a GPS receiver or the like. In this case, to vary the frequency of the first IF signal without varying the frequency of the received signal, as with the structure shown in FIG. 6, the reference oscillator side should be structured so that it can vary the frequency as a PLL synthesizer. As a result, two PLL synthesizers are required. Thus, the structure becomes complicated. In addition, the frequency dividing value of the variable frequency divider should be controlled corresponding to the variation of the oscillation frequency of the reference oscillator. Consequently, an institution of the dividing value is complicated and troublesome.
Further, a radio frequency receiver represented by GPS leaks the first IF signal of the radio receiver and causes intermodulations with induced FM broadband radio at near FM broadband stations and nearly frequency band area. Therefore, each other of the radio frequency receiver and other equipments may give an impediment to a receive precision. In particular, since the GPS receiver is composed by a high gain second IF amplifier for the second IF, the problem is remarkable. Therefore, the GPS receiver is currently operated each of areas. However, the GPS receiver can not operate at a special area toward the namely world wide global positioning system. Thus, the GPS receiver should be changed and needed the system composing frequency each by area for taking off the broadband frequency band. Further,a current RF frequency receiver has a problem that a first IF frequency can not independently be varied without unvaried RF frequency and second IF frequency interfacial of the GPS system.